With this service, MacB provides tools, methods and experts with the capability to evaluate FPGA programming files to determine if they do only what is expected in their original specification, datasheet, or hardware description language source – and nothing more. The fdp evaluates previously inaccessible design formats, including FPGA bitstreams and 3rd-party intellectual property (3PIP) circuit cores. The fdp operates on HDL netlists in IEEE standard Verilog format. The result of analysis using this platform are reports that document design deviation from expectations and determine whether those deviations represent the introduction of a system vulnerability. The tools are Linux based and will be available in the TSS environment, along with demonstration material. Training is highly recommended.
fdp: Project Management
The fdp offers a project management structure for automatic task and results organization. A graphical user interface provides users with a visual representation of the design, properties and evaluation progress.
fdp: Transformation and Analysis
The fdp includes tools that transform FPGA designs into simpler structures that improve understanding. This enables users to efficiently analyze designs for triggers, suspicious circuits, and vulnerabilities in the FPGA or IP.
The fdp operates on standard IEEE Verilog compatible with Synopsis, Verdi, OneSpin EC360, leading digital simulators, and other electronic design automation (EDA) and verification tools.
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